This invention relates to an integrated circuit comprising a differential-transistor-pair with MESFETs which are coupled to a supply voltage via a respective load, a node between the respective MESFET and its associated load being coupled to a sub-circuit for controlling the same.
The invention is used, for example, in a latch-type comparator which serves to compare an analog input voltage V.sub.IN with an analog reference voltage V.sub.REF and which is formed by field effect transistors.
The invention can also be used, for example, in a synchronized comparator circuit comprising at least two of these circuits connected in parallel.
As an example, the invention may be used for realizing an analog-to-digital converter which is referred to as a parallel converter and in which the analog input signal is applied to the inputs of several parallel comparator circuits in order to obtain a digital output signal. In the comparator circuits the input voltage is compared with a reference voltage which differs for each comparator circuit. The output signals of the comparator circuits are converted into a digital output signal by means of a decoding device. The synchronized comparator used in such parallel analog comparator circuits generally has a construction as described above.
A circuit of this kind is known, inter alia, from European Patent Application No. 85 201742.5, which corresponds to U.S. Pat. No. 4,649,293 (Mar. 10, 1987).
This U.S. Patent, hereby incorporated by reference, discloses a voltage comparator which is realized by means of transistors, each of which comprises a control terminal, a first main terminal and a second main terminal. The comparator comprises:
an acquisition stage which serves to compare an analog input voltage (V.sub.IN) with an analog reference voltage (V.sub.REF) and to output the comparison result in the form of an intermediate signal (V.sub.M) and its complement (V.sub.M). This stage includes two transistors which constitute a first differential pair. The input voltage (V.sub.IN) and the reference voltage (V.sub.REF) are applied to the respective control terminals of these transistors, whose first main terminals form a connection point which serves to receive a control current and whose second main terminals are coupled, via a respective resistive load, to a first d.c. power supply terminal (V.sub.DD) thus to supply the intermediate signal and its complement, respectively; PA1 a sub-circuit formed as a memory stage which is coupled to the acquisition stage and which serves to produce the logic states determined by the signals supplied by the acquisition stages. The memory stage includes two transistors which form a second differential pair connected clocked bistable storage circuit, the signals supplied by each branch of the acquisition stage being applied to the respective control terminals of these transistors whose first main terminals form a connection point and whose second main terminals are cross-wise coupled to the control terminals of the transistors of the second pair, the latter connection points constituting the outputs of said memory stage. PA1 the connection point of the first differential pair is coupled to a second d.c. power supply terminal V.sub.SS (e.g. ground) via a current source transistor; PA1 the connection point of the second differential pair is connected directly to the potential of the second d.c. power supply terminal V.sub.SS (e.g. ground); PA1 the second differential pair is coupled to a third differential pair which includes two transistors which are connected parallel to the transistors of the second differential pair and whose control terminals receive a clock signal (C).
In the known circuit:
Moreover: the second main terminals of the first differential pair are coupled to the sub-circuit, more particularly to the respective control terminals of the second differential pair, each time via a coupling resistance, and the current source transistor of the first differential pair can be controlled by the clock signal in one version or by a third d.c. supply voltage in a second version.
This known circuit has a number of drawbacks.
First of all, the output conductance of each of the transistors of the acquisition stage, which are field effect transistors of the MESFET type, changes as a function of the frequency.
Consequently, the impedance at the drain of these MESFETs can vary by as much as a factor 3. Thus, in the case of high frequencies this impedance becomes three times lower than in the case of low frequencies.
In the case of a transition, the reference voltage V.sub.REF does not change and the input voltage V.sub.IN is subject to an extremely fast variation so that the current derived from the drain of the transistor receiving the input voltage V.sub.IN assumes a high transitory value corresponding to the conductance of this transistor, which has become very high due to said rapid transition.
Subsequently, the current derived from the drain of the transistor receiving this input voltage V.sub.IN drops to a lower value which corresponds to the static value of the output conductance of this transistor.
In the case of fast switching of V.sub.IN about V.sub.REF, at the electrical level this becomes manifest as low frequency decays of the differential output voltage. As a percentage, such decay may reach 10% of the output dynamics. If, for example, before a switching operation in a state where V.sub.IN .noteq.V.sub.REF the voltage difference between the output and the complementary output is 1 V, after fast switching, during which V.sub.IN has become equal to V.sub.REF, the output and the complementary output maintain a level difference in the order of 0.1 V for a non-negligibly short period of time before assuming the same value.